1. Field of the Invention
This invention relates to the field of integrated circuit memories. More particularly, this invention relates to the driving of word line signals within integrated circuit memories.
2. Description of the Prior Art
It is known to provide integrated circuit memories comprising arrays of bit cells. Word lines carrying word line signals run through these arrays and are used to select a row of bit cells to be accessed. An address of a memory location is input to an integrated circuit memory which decodes this address and determines which word line through an array of bit cells should be driven to an asserted value so that the corresponding row of bit cells may be accessed. As process geometries have become smaller and memory densities higher, problems have arisen in propagation of the word line signal through the array. The word line itself has a finite resistance and capacitance such that it acts as a distributed RC element which slows the word line signal rising to the asserted value when driven by the word line driver circuitry. The problems of the word line signal being too slow to reach its asserted values are made worse when operating at lower operating voltages. Such lower operating voltages are desirable for other reasons, such as power saving. Furthermore, the smaller process geometries tend to suffer from more chip-to-chip variation and even significant amounts of variation due to process, voltage and temperature within an individual chip. The effect of the bit lines running through the array coupling with the word lines also tends to reduce the speed with which the word line signal reaches the asserted value. This coupling with the bit lines also becomes worse as process geometries become smaller. These factors tend to combine to slow the speed with which the word line signal reaches the asserted value and accordingly slow the operation of the memory since an increased amount of time has to be allowed between accesses in order to allow sufficient time to be sure that the word line signal has properly reached its asserted value so that the access required will have been properly performed.
One known way of addressing this problem is to provide word line driver circuitry at each end of a word line passing through an array such that the word line may be driven from each of its ends and so reduce the effect of the distributed resistance and distributed capacitance of the word line. The technique of providing word line drivers at each end of the word line does address the above problems, but suffers from the disadvantage that a second set of word line driver circuitry and associated decoders and control circuitry need to be provided and this consumes an undesirable amount of circuit overhead. In turn, this adversely affects the circuit density of the memory as a whole and tends to increase its cost and power consumption.